Efficient implementation of retiming
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Asymptotically efficient retiming under setup and hold constraints
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Introduction to Algorithms
Retiming with Interconnect and Gate Delay
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Block-based Static Timing Analysis with Uncertainty
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Deriving a new efficient algorithm for min-period retiming
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
An efficient retiming algorithm under setup and hold constraints
Proceedings of the 43rd annual Design Automation Conference
Scalable min-register retiming under timing and initializability constraints
Proceedings of the 45th annual Design Automation Conference
Efficient retiming of large circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Retiming revisited and reversed
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Incorporating interconnect, register, and clock distribution delays into the retiming process
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Retiming edge-triggered circuits under general delay models
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
First-Order Incremental Block-Based Statistical Timing Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Retiming is one of the most powerful sequential transformations that relocates flip-flops in a circuit without changing its functionality. The min-period retiming problem seeks a solution with the minimal clock period. Since most min-period retiming algorithms assume a simple constant delay model that does not take into account many prominent electrical effects in ultra deep sub micron vlsi designs, a general delay model was proposed to improve the accuracy of the retiming optimization. Due to the complexity of the general delay model, the formulation of min-period retiming under such model is based on integer linear programming (ILP). However, because the previous ILP formulation was derived on a dense path graph, it incurred huge storage and running time overhead for the ILP solvers and the application was limited to small circuits. In this paper, we present the iRetILP algorithm to solve the min-period retiming problem efficiently under the general delay model by formulating and solving the ILP problems incrementally. Experimental results show that iRetILP is on average 100x faster than the previous algorithm for small circuits and is highly scalable to large circuits in term of memory consumption and running time.