Computing optimal clock schedules
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
TIM: a timing package for two-phase, level-clocked circuitry
DAC '93 Proceedings of the 30th international Design Automation Conference
Decomposable searching problems and circuit optimization by retiming: two studies in general transformations of computational structures
DELAY: an efficient tool for retiming with realistic delay modeling
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A fresh look at retiming via clock skew optimization
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
The validity of retiming sequential circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Design of a logic synthesis system (tutorial)
DAC '96 Proceedings of the 33rd annual Design Automation Conference
The case for retiming with explicit reset circuitry
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
An improved algorithm for minimum-area retiming
DAC '97 Proceedings of the 34th annual Design Automation Conference
Integrating logic retiming and register placement
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Reencoding for cycle-time minimization under fixed encoding length
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Efficient equivalence checking of multi-phase designs using phase abstraction and retiming
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Performance driven resynthesis by exploiting retiming-induced state register equivalence
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Retiming sequential circuits with multiple register classes
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A practical approach to multiple-class retiming
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Retiming for DSM with area-delay trade-offs and delay constraints
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Marsh: min-area retiming with setup and hold constraints
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
AQUILA: An Equivalence Checking System for Large Sequential Designs
IEEE Transactions on Computers
Retiming-based factorization for sequential logic optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The case for registered routing switches in field programmable gate arrays
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Efficient minarea retiming of large level-clocked circuits
Proceedings of the conference on Design, automation and test in Europe
On speeding up extended finite state machines using catalyst circuitry
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Verifying sequential equivalence using ATPG techniques
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Integrated retiming and placement for field programmable gate arrays
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Performance-constrained pipelining of software loops onto reconfigurable hardware
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Optimization of synchronous circuits
Logic Synthesis and Verification
Placement driven retiming with a coupled edge timing model
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Hardware-Software partitioning and pipelined scheduling of transformative applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variables bounding based retiming algorithm
Journal of Computer Science and Technology
Wire Retiming for System-on-Chip by Fixpoint Computation
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Performance-driven register insertion in placement
Proceedings of the 2004 international symposium on Physical design
Minimal period retiming under process variations
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Retiming for Wire Pipelining in System-On-Chip
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Retiming with Interconnect and Gate Delay
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Interconnect Planning with Local Area Constrained Retiming
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Experimental analysis of the fastest optimum cycle ratio and mean algorithms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Incremental retiming for FPGA physical synthesis
Proceedings of the 42nd annual Design Automation Conference
Optimal wire retiming without binary search
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
An efficient retiming algorithm under setup and hold constraints
Proceedings of the 43rd annual Design Automation Conference
A new efficient retiming algorithm derived by formal manipulation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An efficient incremental algorithm for min-area retiming
Proceedings of the 45th annual Design Automation Conference
Scalable min-register retiming under timing and initializability constraints
Proceedings of the 45th annual Design Automation Conference
Integration, the VLSI Journal
iRetILP: an efficient incremental algorithm for min-period retiming under general delay model
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Wire retiming as fixpoint computation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient retiming of large circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Retiming for Soft Error Minimization Under Error-Latching Window Constraints
Proceedings of the Conference on Design, Automation and Test in Europe
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Retiming is a technique for optimizing sequential circuits. It repositions the registers in a circuit leaving the combinational cells untouched. The objective of retiming is to find a circuit with the minimum number of registers for a specified clock period. More than ten years have elapsed since Leiserson and Saxe first presented a theoretical formulation to solve this problem for single-clock edge-triggered sequential circuits. Their proposed algorithms have polynomial complexity; however naive implementations of these algorithms exhibit O(n3) time complexitiy and O(n2) space complexity when applied to digital circuits with n combinational cells. This renders retiming ineffective for circuits with more than 500 combinational cells. This paper addresses the implementation issues required to exploit the sparsity of circuit graphs to allow min-period retiming and constrained min-area retiming to be applied to circuits with as many as 10,000 combinational cells. We believe this is the first paper to address these issues and the first to report retiming results for large circuits.