Sequential circuit delay optimization using global path delays
DAC '93 Proceedings of the 30th international Design Automation Conference
Critical path minimization using retiming and algebraic speed-up
DAC '93 Proceedings of the 30th international Design Automation Conference
Re-encoding sequential circuits to reduce power dissipation
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Efficient implementation of retiming
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Scheduling of behavioral VHDL by retiming techniques
EURO-DAC '94 Proceedings of the conference on European design automation
Logic extraction and factorization for low power
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
DELAY: an efficient tool for retiming with realistic delay modeling
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
The validity of retiming sequential circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Architectural retiming: pipelining latency-constrained circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Retiming sequential circuits for low power
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Performance optimization of sequential circuits by eliminating retiming bottlenecks
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Delay Prediction for Technology-Independent Logic Equations
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Optimizing power using transformations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Common-case computation: a high-level technique for power and performance optimization
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Optimization of synchronous circuits
Logic Synthesis and Verification
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Current sequential optimization techniques apply a variety of logic transformations that mainly target the combinational logic component of the circuit. Retiming is typically applied as a postprocessing step to the gate-level implementation obtained after technology mapping. This paper introduces a new sequential logic transformation which integrates retiming with logic transformations at the technology-independent level. This transformation is based on implicit retiming across logic blocks and fanout stems during logic optimization. Its application to sequential network synthesis results in the optimization of logic across register boundaries. It can be used in conjunction with any measure of circuit quality for which a fast and reliable gain estimation method can be obtained. We immplemented our new technique within the SIS framework and demonstrated its effectiveness in terms of cycle-time minimization on a set sequential benchmark circuits.