The collected works of J. Richard Bu¨chi
The collected works of J. Richard Bu¨chi
IEEE Transactions on Computers
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Sequential circuit delay optimization using global path delays
DAC '93 Proceedings of the 30th international Design Automation Conference
Efficient implementation of retiming
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Permissible observability relations in FSM networks
DAC '94 Proceedings of the 31st annual Design Automation Conference
On test set preservation of retimed circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
DELAY: an efficient tool for retiming with realistic delay modeling
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
The validity of retiming sequential circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Multi-level logic optimization of FSM networks
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Architectural retiming: pipelining latency-constrained circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
The case for retiming with explicit reset circuitry
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Fixed-phase retiming for low power design
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
The maximum set of permissible behaviors for FSM networks
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Input don't care sequences in FSM networks
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Retiming sequential circuits for low power
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Synthesis of finite state machines: logic optimization
Synthesis of finite state machines: logic optimization
Low power logic synthesis under a general delay model
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Using precomputation in architecture and logic resynthesis
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Asymptotically efficient retiming under setup and hold constraints
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Retiming-based factorization for sequential logic optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
Solution of parallel language equations for logic synthesis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Min-area retiming on flexible circuit structures
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Partitioning Sequential Circuits for Logic Optimization
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Verification of I/O Trace Set Inclusion for a Class of Non-Deterministic Finite State Machines
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Mona & Fido: The Logic-Automaton Connection in Practice
CSL '97 Selected Papers from the11th International Workshop on Computer Science Logic
On the performance of level-clocked circuits
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Algebraic structure theory of sequential machines (Prentice-Hall international series in applied mathematics)
Efficient retiming of large circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Implicit computation of compatible sets for state minimization of ISFSMs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Symbolic two-level minimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The state reduction of nondeterministic finite-state machines
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Theory and algorithms for state minimization of nondeterministic FSMs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Sequential synthesis using S1S
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We study techniques for optimizing synchronous sequential circuits. These techniques use either state-based or structural gate-level models. We survey recent advances in state-based techniques focusing on the computation of the flexibility in synthesizing or resynthesizing a node in a network of Finite State Machines. We then survey structural sequential optimization techniques that either relocate registers within the circuit (retiming) or that modify both register placement and the circuit's combinational logic.