Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Transition density, a stochastic measure of activity in digital circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Logic decomposition during technology mapping
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Inaccuracies in power estimation during logic synthesis
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Switching activity estimation using limited depth reconvergent path analysis
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Low power multiplexer decomposition
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Low power logic synthesis for XOR based circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
An exact gate decomposition algorithm for low-power technology mapping
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Computer-Aided Design Techniques for Low Power Sequential Logic Circuits
Computer-Aided Design Techniques for Low Power Sequential Logic Circuits
Low Power Digital CMOS Design
Automated phase assignment for the synthesis of low power domino circuits
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Optimization of synchronous circuits
Logic Synthesis and Verification
Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Till now most efforts in low power lo gic synthesis have oncentr ated on minimizing the total switching activity of a circuit under a zero delay model. This simplification ignor es the effe cts of glitch tr ansitions which may contribute as much as 30% of the total power c onsumption of a circuit. Hence, low power logic synthesis techniques which optimize power under a zer o delay model ar e often not successful in attaining “r eal” p ower savings as measured under a more accurate gener al delay model. In pr actice, to ac curately estimate the switching activity in a circuit under a gener al delay model can be computationally expensive. Hence, to repeatedly call accurate but slow power estimation tools to dir ect the synthesis flow is not a viable approach in the design of low power synthesis tools. In this pap er we take advantage of a fast method for estimating the total switching activity in a circuit under a general delay model to synthesize low power circuits. Sp ecific ally,we use the appr oximation as a basis for algorithms that solve two problems: (1) low power te chnolo gy decomposition of gates under a gener al delay model (2) low power r etiming of sequential cir cuits under a general delay model.