Introduction to algorithms
Technology decomposition and mapping targeting low power dissipation
DAC '93 Proceedings of the 30th international Design Automation Conference
Surveys in combinatorics, 1993
Surveys in combinatorics, 1993
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The Art of Computer Programming Volumes 1-3 Boxed Set
The Art of Computer Programming Volumes 1-3 Boxed Set
Decomposition of logic functions for minimum transition activity
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Exact Gate Decomposition for Low-Power Technology Mapping
Exact Gate Decomposition for Low-Power Technology Mapping
Low power logic synthesis under a general delay model
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis
Proceedings of the 37th Annual Design Automation Conference
Optimal low powerX OR gate decomposition
Proceedings of the 37th Annual Design Automation Conference
A Power Minimization Technique for Arithmetic Circuits by Cell Selection
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
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With the remarkable growth of portable application and the increasing frequency and integration density, power is being given comparable weight to speed and area in IC designs. In technology mapping, how decomposition is done can have a significant impact on the power dissipation of the final implementation. In the literature, only heuristic algorithms are given for the low-power gate decomposition problem. In this paper, we prove many properties an optimal decomposition tree must have. Based on these optimality properties, we design an efficient exact algorithm to solve the low-power gate decomposition problem. Moreover, the exact algorithm can be easily modified to a heuristic algorithm which performs much better than the known heuristics.