Technology decomposition and mapping targeting low power dissipation
DAC '93 Proceedings of the 30th international Design Automation Conference
Surveys in combinatorics, 1993
Surveys in combinatorics, 1993
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Multilevel logic synthesis for arithmetic functions
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Low power logic synthesis for XOR based circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
An exact gate decomposition algorithm for low-power technology mapping
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Logic Synthesis and Optimization
Logic Synthesis and Optimization
Power minimization of FPRM functions based on polarity conversion
Journal of Computer Science and Technology
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With the remarkable growth of portable application and the increasing frequency and integration density, power is being given comparable weight to speed and area in IC designs. For the problem of low power decomposition of an XOR gate, if the implementation technology is static CMOS logic, previous research gave an O(n) log (n) time algorithm which assumes that the inputs have both polarities available. But that approach can not be used in dynamic logic. In this paper, we analyze the properties of optimal XOR decompositions in dynamic logic. Based on these optimality properties, we design an optimal algorithm to solve the low power XOR decomposition problem in dynamic logic. We also point out that the previous solution for static logic is not optimal, and give an optimal algorithm which does not even change the input polarities.