Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Technology decomposition and mapping targeting low power dissipation
DAC '93 Proceedings of the 30th international Design Automation Conference
Surveys in combinatorics, 1993
Surveys in combinatorics, 1993
DAC '94 Proceedings of the 31st annual Design Automation Conference
Multilevel logic synthesis for arithmetic functions
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Low power multiplexer decomposition
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Technology-dependent transformations for low-power synthesis
DAC '97 Proceedings of the 34th annual Design Automation Conference
Logic Synthesis and Optimization
Logic Synthesis and Optimization
Low power logic synthesis under a general delay model
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Automated phase assignment for the synthesis of low power domino circuits
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis
Proceedings of the 37th Annual Design Automation Conference
Optimal low powerX OR gate decomposition
Proceedings of the 37th Annual Design Automation Conference
Power minimization of FPRM functions based on polarity conversion
Journal of Computer Science and Technology
Synthesizing complementary circuits automatically
Proceedings of the 2009 International Conference on Computer-Aided Design
Synthesizing complementary circuits automatically
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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An abundance of research efforts in low power logic synthesis have so far been focused on AND/OR or NAND/NOR based logic. A typical approach is to first generate an initial multi- level AND/OR or NAND/NOR representation of a boolean function. Next, the representation is optimized in terms of power. However, there are major classes of circuits such as arithmetic functions which have sizable AND/OR representations but have very compact AND/XOR representations. For these functions AND/OR based optimization approach often yields poor results. In this paper, we put forth a paradigm for low power logic synthesis based on AND/XOR representations of boolean functions. Specifically, we propose transforming a boolean function into a Fixed Polarity Reed Muller form that allows us to efficiently synthesize XOR trees and AND trees with provably minimum switching activity. Preliminary experimental results show that we attain good power savings with negligible area overhead and often area reduction when compared to conventional AND/XOR based synthesis methods and the Berkeley SIS system.