High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Low power logic synthesis for XOR based circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
An exact gate decomposition algorithm for low-power technology mapping
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Optimal allocation of carry-save-adders in arithmetic optimization
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Optimizing power using transformations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Improved merging of datapath operators using information content and required precision analysis
Proceedings of the 38th annual Design Automation Conference
Integrated algorithmic logical and physical design of integer multiplier
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Optimizing high speed arithmetic circuits using three-term extraction
Proceedings of the conference on Design, automation and test in Europe: Proceedings
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Wallace-tree compressor style has been widely recognized as one of the most effective implementation schemes for arithmetic computation sin VLSI design. However, the scheme has been applied only in a rather restrictive way, that is, for implementing fast multipliers and for generating fixed structures without considering the characteristic of the input signals. The contributions of our work are (1) to extend the applicability of the Wallace scheme to any arithmetic circuit which consists of additions/substractions/multiplications globally (instead of applying it to each operation) to produce a globally efficient architecture of the circuit; (2) to optimize the timing of the circuit for uneven signal arrival profiles; (Specifically, we present an efficient algorithm for generating a delay-optimal (bit-level) carry-save addition structure of an arithmetic circuit.) (3) to provide a comprehensive analysis of the switching activity of a (bit-level) carry-save addition structure, and based on which we derive an effective algorithm for synthesizing low power circuits. Putting these arithmetic optimization solutions together, a circuit designer will be able to fully understand the synthesis of arithmetic circuit based on the bit-level carry-save addition.