Incremental tree height reduction for high level synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Arithmetic optimization using carry-save-adders
DAC '98 Proceedings of the 35th annual Design Automation Conference
Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis
Proceedings of the 37th Annual Design Automation Conference
Optimal allocation of carry-save-adders in arithmetic optimization
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A timing-driven synthesis of arithmetic circuits using carry-save-adders (short paper)
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Layout-aware synthesis of arithmetic circuits
Proceedings of the 39th annual Design Automation Conference
Digital Signal Processing: A Computer-Based Approach
Digital Signal Processing: A Computer-Based Approach
Common Subexpression Elimination Involving Multiple Variables for Linear DSP Synthesis
ASAP '04 Proceedings of the Application-Specific Systems, Architectures and Processors, 15th IEEE International Conference
Improved use of the carry-save representation for the synthesis of complex arithmetic circuits
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Area optimization algorithms in high-speed digital FIR filter synthesis
Proceedings of the 21st annual symposium on Integrated circuits and system design
Comments on 'A 70 MHz Multiplierless FIR Hilbert Transformer in 0.35 μm Standard CMOS Library'
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Xquasher: a tool for efficient computation of multiple linear expressions
Proceedings of the 46th Annual Design Automation Conference
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Carry Save Adder (CSA) trees are commonly used for high speed implementation of multi-operand additions. We present a method to reduce the number of the adders in CSA trees by extracting common three-term subexpressions. Our method can optimize multiple CSA trees involving any number of variables. This optimization has a significant impact on the total area of the synthesized circuits, as we show in our experiments. To the best of our knowledge, this is the only known method for eliminating common subexpressions in CSA structures. Since extracting common subexpressions can potentially increase delay, we also present a delay aware extraction algorithm that takes into account the different arrival times of the signals.