Computer arithmetic systems: algorithms, architecture and implementation
Computer arithmetic systems: algorithms, architecture and implementation
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Optimal Circuits for Parallel Multipliers
IEEE Transactions on Computers
Term rewriting and all that
Maximally fast and arbitrarily fast implementation of linear computations
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits
IEEE Transactions on Computers
Improved merging of datapath operators using information content and required precision analysis
Proceedings of the 38th annual Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Symbolic algebra and timing driven data-flow synthesis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Arithmetic Transformations to Maximise the Use of Compressor Trees
DELTA '04 Proceedings of the Second IEEE International Workshop on Electronic Design, Test and Applications
Circuit optimization using carry-save-adder cells
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Bitwidth cognizant architecture synthesis of custom hardware accelerators
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal joint module-selection and retiming with carry-save representation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exploiting Vanishing Polynomials for Equivalence Veri.cation of Fixed-Size Arithmetic Datapaths
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Equivalence verification of arithmetic datapaths with multiple word-length operands
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Optimizing high speed arithmetic circuits using three-term extraction
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Towards the automatic exploration of arithmetic-circuit architectures
Proceedings of the 43rd annual Design Automation Conference
Automatic synthesis of compressor trees: reevaluating large counters
Proceedings of the conference on Design, automation and test in Europe
Optimization of polynomial datapaths using finite ring algebra
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Enhancing FPGA performance for arithmetic circuits
Proceedings of the 44th annual Design Automation Conference
Progressive decomposition: a heuristic to structure arithmetic circuits
Proceedings of the 44th annual Design Automation Conference
Finding linear building-blocks for RTL synthesis of polynomial datapaths with fixed-size bit-vectors
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A novel FPGA logic block for improved arithmetic performance
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Efficient synthesis of compressor trees on FPGAs
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Improving synthesis of compressor trees on FPGAs via integer linear programming
Proceedings of the conference on Design, automation and test in Europe
Area optimization algorithms in high-speed digital FIR filter synthesis
Proceedings of the 21st annual symposium on Integrated circuits and system design
Design space exploration for field programmable compressor trees
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Verification of arithmetic datapaths using polynomial function models and congruence solving
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Code transformation and instruction set extension
ACM Transactions on Embedded Computing Systems (TECS)
Simulation bounds for equivalence verification of polynomial datapaths using finite ring algebra
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Frequent-pattern-guided multilevel decomposition of behavioral specifications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A timing-driven hybrid-compression algorithm for faster Sum-of-Products
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
Algebraic techniques to enhance common sub-expression elimination for polynomial system synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
High performance and area efficient flexible DSP datapath synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The increasing importance of datapath circuits in complex systems-on-chip calls for special arithmetic optimisations. The goal is to achieve automatically the handcrafted results which escape classic logic optimisations. Some work has been done in the recent years to infer the use of the carry-save representation in the synthesis of arithmetic circuits. Yet, many cases of practical interest cannot be handled due to the scattering of logic operations among the arithmetic ones - especially in arithmetic computations which are originally described at the bit level in high-level languages such as C. We therefore introduce an algorithm to restructure dataflow graphs so that they can be synthesized in high-quality arithmetic circuits, close, to those that an expert designer would conceive. On typical embedded software benchmarks which could be advantageously implemented with hardware accelerators, our technique always reduces tangibly the critical path by up to 46% and generally achieves the quality of manual implementations. In many cases, our algorithm also manages to reduce the cell area by up to 10-20%.