Design space exploration for field programmable compressor trees

Authors:
Seyed Hosein Attarzadeh Niaki;Alessandro Cevrero;Philip Brisk;Chrysostomos Nicopoulos;Frank K. Gurkaynak;Yusuf Leblebici;Paolo Ienne
Affiliations:
Royal Institute of Technology, Stockholm, Sweden;Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland;Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland;Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland;Swiss Federal Institute of Technology, Zurich, Zurich, Switzerland;Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland;Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland
Venue:
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Year:
2008

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Abstract

The Field Programmable Compressor Tree (FPCT) is a programmable compressor tree (e.g., a Wallace or Dadda Tree) intended for integration in an FPGA or other reconfigurable device. This paper presents a design space exploration (DSE) method that can be used to identify the best FPCT architecture for a given set of arithmetic benchmark circuits; in practice, an FPGA vendor can use the design space exploration to tailor the FPCT to meet the needs of the most important benchmark circuits of the vendor's largest-volume clients. One novel feature of the DSE is the introduction of a metric called I/O utilization; we found that I/O utilization has a strong correlation with both the critical path delay and area of the benchmark circuits under study. Pruning the search space using I/O utilization allowed us to reduce significantly the number of FPCTs that must be synthesized and evaluated during the DSE, while giving high confidence that the best architectures are still explored. The DSE was applied to seven small-to-medium range benchmark circuits; one FPCT architecture was found that was 30% faster than the second best in terms of critical path delay, and only 3.34% larger than the smallest.