Multiple Operand Addition and Multiplication
IEEE Transactions on Computers
An Iterative Array for Multiplication of Signed Binary Numbers
IEEE Transactions on Computers
IEEE Transactions on Computers
Arithmetic Networks and Their Minimization Using a New Line of Elementary Units
IEEE Transactions on Computers
A 40-ns 17-Bit by 17-Bit Array Multiplier
IEEE Transactions on Computers
Adder With Distributed Control
IEEE Transactions on Computers
Synthesis and Comparison of Two's Complement Parallel Multipliers
IEEE Transactions on Computers
A Two's Complement Parallel Array Multiplication Algorithm
IEEE Transactions on Computers
Multiple Addition by Residue Threshold Functions and Their Representation by Array Logic
IEEE Transactions on Computers
Algorithms for Iterative Array Multiplication
IEEE Transactions on Computers
An Array Layout Methodology for VLSI Circuits
IEEE Transactions on Computers
Minimum Mean Running Time Function Generation Using Read-Only Memory
IEEE Transactions on Computers
A Digital Quarter Square Multiplier
IEEE Transactions on Computers
Arithmetic for Ultra-High-Speed Tomography
IEEE Transactions on Computers
Synthesis of Generalized Parallel Counters
IEEE Transactions on Computers
A Two's Complement Array Multiplier Using True Values of the Operands
IEEE Transactions on Computers
A Canonical Bit-Sequential Multiplier
IEEE Transactions on Computers - Lecture notes in computer science Vol. 174
An Upper Bound for the Synthesis of Generalized Parallel Counters
IEEE Transactions on Computers - Lecture notes in computer science Vol. 174
IEEE Transactions on Computers
IEEE Transactions on Computers
A novel FPGA logic block for improved arithmetic performance
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Efficient synthesis of compressor trees on FPGAs
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Design space exploration for field programmable compressor trees
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
An FPGA Logic Cell and Carry Chain Configurable as a 6:2 or 7:2 Compressor
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Improving FPGA performance for carry-save arithmetic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-operand adder synthesis on FPGAs using generalized parallel counters
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Compressor tree synthesis on commercial high-performance FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
| Hi-index | 15.01 |
This paper discusses a compact, fast, parallel multiplication scheme of the generation-reduction type using generalized Dadda-type pseudoadders for reduction and m X m multipliers for generation. The implications of present and future LSI are considered, a partitioning algorithm is presented, and the results obtained for a 24 X 24-bit implementation are discussed.