The cube-connected cycles: a versatile network for parallel computation
Communications of the ACM
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Fundamentals of Computer Alori
Fundamentals of Computer Alori
How to assemble tree machines (Extended Abstract)
STOC '82 Proceedings of the fourteenth annual ACM symposium on Theory of computing
Bounds on minimax edge length for complete binary trees
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
A complexity theory for VLSI
Area-efficient vlsi computation
Area-efficient vlsi computation
Computational Aspects of VLSI
Graph Theory with Applications to Engineering and Computer Science (Prentice Hall Series in Automatic Computation)
A Regular Layout for Parallel Adders
IEEE Transactions on Computers
The Binary Tree as an Interconnection Network: Applications to Multiprocessor Systems and VLSI
IEEE Transactions on Computers
Tree Realizations of Iterative Circuits
IEEE Transactions on Computers
A Compact High-Speed Parallel Multiplication Scheme
IEEE Transactions on Computers
A Survey of Interconnection Networks
Computer
Applications of a planar separator theorem
SFCS '77 Proceedings of the 18th Annual Symposium on Foundations of Computer Science
An area-time efficient NMOS adder
Integration, the VLSI Journal
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A new methodology for the layout design of several classes of useful VLSI structures is proposed. The approach produces a structured layout for commonly found computation structures, using regular elements called layout slices. Algorithms for optimal array realization are described that offer several significant advantages over existing layout schemes. Any network that can be decomposed into instances of these structures can therefore be realized using layout slices. Algorithms for the array realization of a class of arbitrary networks are also described. Several well-known structures such as trees, carry-save adders and cube-connected cycles can be realized using the proposed array layout methodology, not only with optimal area but also with several features necessary for practical implementation, e.g., access to key nodes, high area utilization and global signal routing. The proposed methodology is illustrated with actual layouts of useful circuits.