On the Time Required to Perform Addition
Journal of the ACM (JACM)
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
Introduction to VLSI Systems
Structure of Computers and Computations
Structure of Computers and Computations
The chip complexity of binary arithmetic
STOC '80 Proceedings of the twelfth annual ACM symposium on Theory of computing
A Regular Layout for Parallel Adders
IEEE Transactions on Computers
On the Addition of Binary Numbers
IEEE Transactions on Computers
A Survey of Some Recent Contributions to Computer Arithmetic
IEEE Transactions on Computers
An Array Layout Methodology for VLSI Circuits
IEEE Transactions on Computers
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A model of computation for VLSI systems has been developed based on the Mead and Conway approach. This model accommodates the fan-out dependency in NMOS technology. Based on this model, a method for producing area-time efficient carry lookahead adders in NMOS has been developed. This method coordinates between the structural level (cells and interconnections) and the physical layout level (size of individual transistor). The proposed procedure exhibits modularity and regularity. Finally, an example of designing a 4-bit adder is given.