The logic of computer arithmetic
The logic of computer arithmetic
An Array Layout Methodology for VLSI Circuits
IEEE Transactions on Computers
IEEE Transactions on Computers
The Fastest Multiplier on FPGAs with Redundant Binary Representation
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Delay-Insensitive Carry-Lookahead Adders
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Area-Time Optimal Fast Implementation of Several Functions in a VLSI Model
IEEE Transactions on Computers
The generation of completion signals in iterative combinational circuits
IEEE Transactions on Computers
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It is shown how any combinational function that can be described by a flow table or equivalently is realizable in iterative form can be realized in tree form. The propagation delay is then proportional to the logarithm of n, the number of inputs, while the logic complexity is a linear function of n. These results are related to various implementations of high-speed binary adders and a proposed new high-speed adder circuit.