Communications of the ACM
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
The limitations to delay-insensitivity in asynchronous circuits
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
The logic of computer arithmetic
The logic of computer arithmetic
A Regular Layout for Parallel Adders
IEEE Transactions on Computers
Tree Realizations of Iterative Circuits
IEEE Transactions on Computers
Some New Results on Average Worst Case Carry
IEEE Transactions on Computers
Conditional-Sum Early Completion Adder Logic
IEEE Transactions on Computers
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Integer addition is one of the mast important operations in digital computer systems because the performance of processors is significantly influenced by the speed of their adders. This paper proposes a delay insensitive, carry-lookahead adder in which the logic complexity is a linear function of n, the number of inputs, and the average computation time is proportional to the logarithm of the logarithm of n. We also show an economic implementation of this adder in CMOS technology.