Computer structures: Readings and examples (McGraw-Hill computer science series)
Computer structures: Readings and examples (McGraw-Hill computer science series)
Activity-Monitoring Completion-Detection (AMCD): A New Single Rail Approach to Achieve Self-Timing
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Delay-Insensitive Carry-Lookahead Adders
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
The average time complexity to compute preffix functions in processor networks
STACS'99 Proceedings of the 16th annual conference on Theoretical aspects of computer science
Arithmetic data value speculation
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Hi-index | 14.98 |
The previous bound on average worst case carry in a two's complement adder found by Burks et al. [1] is tightened, a bound is established for one's complement adders, and exact expressions for average worst case carry are derived and "experimentally" tested. It is found that an n-bit ripple-carry two's complement adder with carry-completion detection is potentially as fast, on the average, as the old bound indicated an n/v2-bit adder of the same kind would be.