Limits of instruction-level parallelism
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
Performance improvement with circuit-level speculation
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Computer Architecture: A Quantitative Approach
Computer Architecture: A Quantitative Approach
Some New Results on Average Worst Case Carry
IEEE Transactions on Computers
Increasing throughput of a RISC architecture using arithmetic data value speculation
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
Function approximation based on estimated arithmetic operators
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
Modeling and synthesis of quality-energy optimal approximate adders
Proceedings of the International Conference on Computer-Aided Design
High performance reliable variable latency carry select addition
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Value speculation is currently widely used in processor designs to increase the overall number of instructions executed per cycle (IPC). Current methods use sophisticated prediction techniques to speculate on the outcome of branches and execute code accordingly. Speculation can be extended to the approximation of arithmetic values. As arithmetic operations are slow to complete in pipelined execution an increase in overall IPC is possible through accurate arithmetic data value speculation. This paper will focus on integer adder units for the purposes of demonstrating arithmetic data value speculation.