Practical advances in asynchronous design and in asynchronous/synchronous interfaces
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Statistically optimized asynchronous barrel shifters for variable length codecs
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
An asynchronous matrix-vector multiplier for discrete cosine transform
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Logic Synthesis and Verification
A New Methodology to Design Low-Power Asynchronous Circuits
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
A Counterflow Pipeline Experiment
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Asynchronous Microengines for Efficient High-level Control
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
A High-Speed Asynchronous Decompression Circuit for Embedded Processors
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Journal of Systems Architecture: the EUROMICRO Journal
A fast, energy-efficient z-comparator
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Minimal energy asynchronous dynamic adders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A variation-tolerant scheduler for better than worst-case behavioral synthesis
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
A low-voltage micropower asynchronous multiplier with shift-add multiplication approach
IEEE Transactions on Circuits and Systems Part I: Regular Papers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A new speculative addition architecture suitable for two's complement operations
Proceedings of the Conference on Design, Automation and Test in Europe
Variable-latency design by function speculation
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the International Conference & Workshop on Emerging Trends in Technology
Architectural optimization for low-power nonpipelined asynchronous systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Arithmetic data value speculation
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
High performance reliable variable latency carry select addition
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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This paper presents an in-depth case study in high-performance asynchronous adder design. A recent method, called "speculative completion", is used. This method uses single-rail bundled datapaths but also allows early completion. Five new dynamic designs are presented for Brent-Kung and Carry-Bypass adders. Furthermore, two new architectures are introduced, which target (i) small number addition, and (ii) hybrid operation. Initial SPICE simulation and statistical analysis show performance improvements up to 19% on random inputs and 14% on actual programs for 32-bit adders, and up to 29% on random inputs for 64-bit adders, over comparable synchronous designs.