Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
RAPPID: An Asynchronous Instruction Length Decoder
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Eliminating the Z-Buffer bottleneck
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Energy Efficient Comparators for Superscalar Datapaths
IEEE Transactions on Computers
BitSNAP: Dynamic Significance Compression for a Low-Energy Sensor Network Asynchronous Processor
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
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We present a fast and energy-efficient z-comparator that takes advantage of the fact that the result of most depth comparisons can be determined by examining just a few bits. This feature is made possible by the use of asynchronous logic, which enables the comparator to rapidly compare bits until the result is clear and then stop. Using depth data from well-known computer games, SPICE simulations indicate that our comparator consumes only 25% of the energy and operates 1.67 times faster, on average, compared to an equivalent synchronous design. The comparator design is used to illustrate a more general design principle, "compute on demand," which can potentially enable graphics hardware to be faster and more energy-efficient.