A fast, energy-efficient z-comparator
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware
Proceedings of the 2005 joint conference on Smart objects and ambient intelligence: innovative context-aware services: usages and technologies
Design of 100 μW Wireless Sensor Nodes for Biomedical Monitoring
Journal of Signal Processing Systems
An accelerator-based wireless sensor network processor in 130nm CMOS
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
Design of 100 µW wireless sensor nodes on energy scavengers for biomedical monitoring
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
Low power programmable architecture for periodic activity monitoring
Proceedings of the ACM/IEEE 4th International Conference on Cyber-Physical Systems
SN-SEC: a secure wireless sensor platform with hardware cryptographic primitives
Personal and Ubiquitous Computing
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We present a novel asynchronous processor architecture called BitSNAP that utilizes bit-serial datapaths with dynamic significance compression to yield extremely low-energy consumption. Based on the Sensor Network Asynchronous Processor (SNAP) ISA, BitSNAP can reduce datapath energy consumption by 50% over a comparable parallel-word processor, while still providing performance suited for powering low-energy sensor network nodes. In 180nm CMOS, the processor is expected to run at between 6 and 54 MIPS while consuming 152pJ/ins at 1.8V and just 17pJ/ins at 0.6V.