Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Low-power operation using self-timed circuits and adaptive scaling of the supply voltage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Transistor reordering rules for power reduction in CMOS gates
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Processor design for portable systems
Journal of VLSI Signal Processing Systems - Special issue on technologies for wireless computing
Fast Combinatorial RNS Processors for DSP Applications
IEEE Transactions on Computers
ET2: a metric for time and energy efficiency of computation
Power aware computing
A Low-power Asynchronous Data-path for a FIR Filter Bank
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
The Lutonium: A Sub-Nanojoule Asynchronous 8051 Microcontroller
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Designing CMOS Circuits for Low Power
Designing CMOS Circuits for Low Power
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
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In battery-operated portable or implantable digital devices, where battery life needs to be maximized, it is necessary to minimize not only power consumption but also energy dissipation. Typical energy optimization measures include voltage reduction and operating at the slowest possible speed. We employ additional methods, including hybrid asynchronous dynamic design to enable operating over a wide range of battery voltage, aggregating large combinational logic blocks, and transistor sizing and reordering. We demonstrate the methods on simple adders, and discuss extension to other circuits. Three novel adders are proposed and analyzed: a 2-bit pass transistor logic (PTL) adder and two dynamic 2-bit adders. Circuit simulations on a 0.18-µm process at low voltage show that leakage energy is below 1%. The proposed adders achieve up to 40 % energy savings relative to previously published results, while also operating faster.