The design of an asynchronous microprocessor
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
Towards an energy complexity of computation
Information Processing Letters - Special issue in honor of Edsger W. Dijkstra
ET2: a metric for time and energy efficiency of computation
Power aware computing
An Asynchronous Low-Power 80C51 Microcontroller
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
The Design of an Asynchronous MIPS R3000 Microprocessor
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Energy-delay complexity of asychronous circuits
Energy-delay complexity of asychronous circuits
High-level synthesis of asynchronous systems by data-driven decomposition
Proceedings of the 40th annual Design Automation Conference
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
An ultra low-power processor for sensor networks
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Design of a cell library for asynchronous microengines
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
An asynchronous low-power high-performance sequential decoder implemented with QDI templates
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Minimal energy asynchronous dynamic adders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Using standard asic back-end for qdi asynchronous circuits: dealing with isochronic fork constraint
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Design automation of real-life asynchronous devices and systems
Foundations and Trends in Electronic Design Automation
Design of dual threshold voltages asynchronous circuits
Proceedings of the 13th international symposium on Low power electronics and design
High performance asynchronous design flow using a novel static performance analysis method
Computers and Electrical Engineering
Optimal sleep/wake scheduling for time-synchronized sensor networks with QoS guarantees
IEEE/ACM Transactions on Networking (TON)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Process variation-aware performance analysis of asynchronous circuits
Microelectronics Journal
Asynchronous ARM processor employing an adaptive pipeline architecture
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
Statistical leakage power optimization of asynchronous circuits considering process variations
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Proceedings of the International Conference & Workshop on Emerging Trends in Technology
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Power consumption reduction using dynamic control of micro processor performance
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Low power techniques applied to a 80c51 microcontroller for high temperature applications
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Design of asynchronous embedded processor with new ternary data encoding scheme
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
VLSI implementation of a distributed algorithm for fault-tolerant clock generation
Journal of Electrical and Computer Engineering - Special issue on Clock/Frequency Generation Circuits and Systems
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We describe the Lutonium, an asynchronous 8051 microcontroller designed for low Et2. In 0.18-µm CMOS, at nominal 1.8 V, we expect a performance of 0.5 nJ per instruction at 200 MIPS. At 0.5 V, we expect 4 MIPS and 40J/instruction, corresponding to 25,000 MIPS/Watt. We describe the structure of a fine-grain pipeline optimized for Et2 efficiency, some of the peripherals implementation, and the advantages of an asynchronous implementation of a deep-sleep mechanism.