Power consumption reduction using dynamic control of micro processor performance

Authors:
David Rios-Arambula;Aurélien Buhrig;Marc Renaudin
Affiliations:
TIMA Laboratory, Grenoble Cedex, France;TIMA Laboratory, Grenoble Cedex, France;TIMA Laboratory, Grenoble Cedex, France
Venue:
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2005

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Abstract

An alternative way to reduce power consumption using dynamic voltage scaling is presented. The originality of this approach is the modeling and simulation of a system where each application indicates its performance needs (in MIPS) to the operating system, which in turn is able to know the global speed requirements of the system to meet all real time application deadlines. To achieve this level of control, a co-processor is described, that receives a set point command from the OS, and manages a DC/DC converter implemented as a charge pump, in order to have the system speed fitting this set point. This architecture is especially suited for asynchronous processors but can be adapted for synchronous ones as well.