The Design of an Asynchronous MIPS R3000 Microprocessor

  • Authors:
  • Alain J. Martin;Andrew Lines;Rajit Manohar;Mika Nystroem;Paul Penzes;Robert Southworth;Uri Cummings

  • Affiliations:
  • -;-;-;-;-;-;-

  • Venue:
  • ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
  • Year:
  • 1997

Quantified Score

Hi-index 0.01

Visualization

Abstract

The design of an asynchronous clone of a MIPS R3000 microprocessor is presented. In 0.6 micron CMOS, we expect performance close to 280 MIPS, for a power consumption of 7 Watts. The paper describes the structure of a high- performance asynchronous pipeline, in particular precise exceptions, pipelined caches, arithmetic, and registers, and the circuit techniques developed to achieve high frequency.