CMOS design of the tree arbiter element
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Lowering power consumption in clock by using globally asynchronous locally synchronous design style
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Modular Asynchronous Arbiter Insensitive to Metastability
IEEE Transactions on Computers
The design of easily scalable bus arbiters with different dynamic priority assignment schemes
ASILOMAR '95 Proceedings of the 29th Asilomar Conference on Signals, Systems and Computers (2-Volume Set)
Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
Point to Point GALS Interconnect
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Self-Timed Ring for Globally-Asynchronous Locally-Synchronous Systems
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
The Design of an Asynchronous MIPS R3000 Microprocessor
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
TITAC-2: an asynchronous 32-bit microprocessor based on scalable-delay-insensitive model
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems
Proceedings of the conference on Design, automation and test in Europe
Performance, Energy, and Thermal Considerations for SMT and CMP Architectures
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Partitioning Multi-Threaded Processors with a Large Number of Threads
ISPASS '05 Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2005
The "Chimera": an off-the-shelf CPU/GPGPU/FPGA hybrid computing platform
International Journal of Reconfigurable Computing - Special issue on High-Performance Reconfigurable Computing
| Hi-index | 0.00 |
This paper presents a scalable and partitionable asynchrono-us bus arbiter for use with chip multiprocessors (CMP) and its corresponding pre-layout simulation results using VHDL. The arbiter exploits the advantage of a concurrency control instruction (Brk) provided by the micro-threaded microprocessor model to set the priority processor and move the circulated arbitration token at the most likely processor to issue the create instruction. This mechanism provides latency hiding during token circulation by decoupling the micro-threaded processor from the ring's timing. It is shown that this arbiter can be extended easily to support large numbers of processors and can be used for chip multiprocessor arbitration purposes.