Reliable High-Speed Arbitration and Synchronization
IEEE Transactions on Computers
Q-Modules: Internally Clocked Delay-Insensitive Modules
IEEE Transactions on Computers
Design and Analysis of Arbitration Protocols
IEEE Transactions on Computers
Comments on 'Design and Analysis of Arbitration Protocols' by F. El Guibaly
IEEE Transactions on Computers
Analysis of Metastable Operation in a CMOS Dynamic D-Latch
Analog Integrated Circuits and Signal Processing - Special issue: analog design issues in digital VSLI circuits and systems
Oscillatory Metastability in Optical Network Synchronizer Circuits
The Journal of Supercomputing
Asynchronous arbiter for micro-threaded chip multiprocessors
Journal of Systems Architecture: the EUROMICRO Journal
Scalable and partitionable asynchronous arbiter for micro-threaded chip multiprocessors
ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems
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The purpose of this paper is to present a novel modular N-user asynchronous arbiter circuit which is insensitive to metastable operation (i.e., the new arbiter cannot fail because of metastability), operating asynchronously and incorporating a modular architecture. A 1.5驴m CMOS prototype arbiter has been designed and tested. Laboratory tests demonstrate the arbiter operates correctly.