Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
Introduction to VLSI Systems
Communications of the ACM
Performance of Synchronous and Asynchronous Schemes for VLSI Systems
IEEE Transactions on Computers
Designing an Asynchronous Communications Chip
IEEE Design & Test
TITAC: Design of A Quasi-Delay-Insensitive Microprocessor
IEEE Design & Test
Externally hazard-free implementations of asynchronous circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
High Speed Externally Asynchronous/ Internally Clocked Systems
IEEE Transactions on Computers
A methodology for correct-by-construction latency insensitive design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
What is the cost of delay insensitivity?
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
An FPGA for Implementing Asynchronous Circuits
IEEE Design & Test
Developing Micropipeline Wavefront Arbiters
IEEE Design & Test
Hazards, Critical Races, and Metastability
IEEE Transactions on Computers
Modular Asynchronous Arbiter Insensitive to Metastability
IEEE Transactions on Computers
Specification and Validation of Control-Intensive IC's in hopCP
IEEE Transactions on Software Engineering
A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Counterflow Pipeline Based Dynamic Instruction Scheduling
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Low latency self-timed flow-through FIFOs
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Interfacing Synchronous and Asynchronous Modules Within a High-Speed Pipeline
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Synchro-Tokens: A Deterministic GALS Methodology for Chip-Level Debug and Test
IEEE Transactions on Computers
Reasoning about synchronization in GALS systems
Formal Methods in System Design
ACM Turing award lectures
Pipelining communications in large VLSI/ULSI systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A syntax-directed translation for the synthesis of delay-insensitive circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 15.01 |
Q-modules are internally clocked modules that can be used to satisfy delay-insensitive specifications. A single delay element is required with a one-sided bound that its value be greater than the maximum delay of the combination logic. Prototypes of components to implement Q-modules have been designed, and a design aid program, QSYN, to place instances of these components, personalize a PLA, and generate a MAGIC or CIF file for a CMOS realization, including the delay circuitry, is being developed. Testability is one of the advantages of Q-modules over clock-free delay-insensitive modules; circuitry is included in the cells for testing the logic and interconnections.