Q-Modules: Internally Clocked Delay-Insensitive Modules
IEEE Transactions on Computers
High-speed digital design: a handbook of black magic
High-speed digital design: a handbook of black magic
Lowering power consumption in clock by using globally asynchronous locally synchronous design style
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Pausible clocking-based heterogeneous systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An On-Chip Dynamically Recalibrated Delay Line for Embedded Self-Timed Systems
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Interfacing Synchronous and Asynchronous Modules Within a High-Speed Pipeline
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Asynchronous Wrapper for Heterogeneous Systems
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Rapid Prototyping of Self-timed Circuits
ICCD '98 Proceedings of the International Conference on Computer Design
Power and performance evaluation of globally asynchronous locally synchronous processors
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Power: A First Class Design Constraint for Future Architecture and Automation
HiPC '00 Proceedings of the 7th International Conference on High Performance Computing
Throughput-driven IC communication fabric synthesis
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Power efficiency of voltage scaling in multiple clock, multiple voltage cores
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Designing an asynchronous microcontroller using pipefitter
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks
IEEE Transactions on Computers
A predictive synchronizer for periodic clock domains
Formal Methods in System Design
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Integration, the VLSI Journal
GALS for Bursty Data Transfer based on Clock Coupling
Electronic Notes in Theoretical Computer Science (ENTCS)
GALS Test Chip on 130nm Process
Electronic Notes in Theoretical Computer Science (ENTCS)
Analysis and optimization of pausible clocking based GALS design
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
High rate data synchronization in GALS socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
International Journal of Embedded and Real-Time Communication Systems
A compact clock generator for heterogeneous GALS MPSoCs in 65-nm CMOS technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present a local clocking mechanism based on a tunable delay line, which calibrates itself from a low frequency global clock. After initial tuning, the local clock remains calibrated when environmental conditions change. Each module of a large system on a chip can use one of these clock generators running at the optimal frequency for the module.Communication between locally synchronous blocks is provided by a globally asynchronous interconnect. Reliable low latency communication between the asynchronous interconnects and a local clock domain is made possible by stretching the local clock if a meta-stable condition could be encountered. Stretching the clock just requires the rising clock edge to be prevented from entering the tuned delay line. Similarly, stopping the clock can enter a sleep state and wakeup is almost instantaneous. Fine grained sleeping is possible by sleeping whenever there is no work to be undertaken and waking up as soon as new data appears over the asynchronous interconnect.