Variable supply-voltage scheme with 95%-efficiency DC-DC converter for MPEG-4 codec
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Pausible clocking-based heterogeneous systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic Voltage Scheduling for Real Time Asynchronous Systems
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Practical Design of Globally-Asynchronous Locally-Synchronous Systems
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Point to Point GALS Interconnect
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Request-Driven GALS Technique for Wireless Communication System
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
GALS at ETH Zurich: Success or Failure
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
Demystifying Data-Driven and Pausible Clocking Schemes
ASYNC '07 Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems
Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Scheduling for reduced CPU energy
OSDI '94 Proceedings of the 1st USENIX conference on Operating Systems Design and Implementation
Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook
IEEE Design & Test
A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling
PATMOS '07 Proceedings of the 17th international workshop on Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
High rate data synchronization in GALS socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design and optimization of multithreshold CMOS (MTCMOS) circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
GALS for Bursty Data Transfer based on Clock Coupling
Electronic Notes in Theoretical Computer Science (ENTCS)
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analysis and optimization of pausible clocking based GALS design
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Networks on Chips: from research to products
Proceedings of the 47th Design Automation Conference
Distributed DVFS using rationally-related frequencies and discrete voltage levels
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs
Proceedings of the Conference on Design, Automation and Test in Europe
Quasi delay-insensitive high speed two-phase protocol asynchronous wrapper for network on chips
Journal of Computer Science and Technology
On line power optimization of data flow multi-core architecture based on vdd-hopping for local DVFS
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Handling dynamic frequency changes in statically scheduled cycle-accurate simulation
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Low-energy GALS NoC with FIFO-Monitoring dynamic voltage scaling
Microelectronics Journal
A self-adaptable distributed DFS scheme for NoC-based MPSoCs
Proceedings of the 24th symposium on Integrated circuits and systems design
Modeling and reducing EMI in GALS and synchronous systems
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Clustered NOC, a suitable design for group communications in Network on Chip
Computers and Electrical Engineering
Power-aware dynamic memory management on many-core platforms utilizing DVFS
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on ESTIMedia'10
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In complex embedded applications, optimization and adaptation at run time of both dynamic and leakage power have become an issue at SoC coarse grain. For power reduction, voltage and frequency scaling techniques have been applied successfully to CPUs but never with a generic approach for all IPs within a SoC. Network-on-Chip architecture combined with a Globally Asynchronous Locally Synchronous paradigm is a natural enabler for easy IP unit integration. GALS NoC provides scalable communications and a clear split between timing domains. We propose in this paper a complete Dynamic Voltage and Frequency Scaling architecture for IP units integration within a GALS NOC. The proposed DVFS architecture is based on the association of Local clock generator and VDD-Hopping between two given voltages. No fine control software is required during any voltage and frequency re-programming. As a result, minimal latency cost is observed. The power efficiency of the proposed system has been evaluated close to 95%.