Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Methods for power optimization in SOC-based data flow systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On line power optimization of data flow multi-core architecture based on vdd-hopping for local DVFS
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Power reduction of asynchronous logic circuits using activity detection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-energy GALS NoC with FIFO-Monitoring dynamic voltage scaling
Microelectronics Journal
Brief announcement: reclaiming the energy of a schedule, models and algorithms
Proceedings of the twenty-third annual ACM symposium on Parallelism in algorithms and architectures
Procedure hopping: a low overhead solution to mitigate variability in shared-L1 processor clusters
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
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In systems-on-chip, dynamic voltage scaling allows energy savings. If only one global voltage is scaled down, the voltage cannot be lower than the voltage required by the most constrained functional unit to meet its timing constraints. Fine-grained dynamic voltage scaling allows better energy savings since each functional unit has its own independent clock and voltage, making the chip globally asynchronous and locally synchronous.In this paper we propose a local dynamic voltage scaling architecture, adapted to globally asynchronous and locally synchronous systems, based on a technique called Vdd-hopping. Compared to traditional power converters, the proposed power supply selector is small and power-efficient, with no needs for large passives or costly technological options. This design has been validated in a STMicroelectronics CMOS 65nm low-power technology.