Run-time voltage hopping for low-power real-time systems
Proceedings of the 37th Annual Design Automation Conference
Energy Aware Scheduling for Distributed Real-Time Systems
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks
IEEE Transactions on Computers
Optimal procrastinating voltage scheduling for hard real-time systems
Proceedings of the 42nd annual Design Automation Conference
DVS for buffer-constrained architectures with predictable QoS-energy tradeoffs
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Speed and voltage selection for GALS systems based on voltage/frequency islands
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A control theoretic approach to run-time energy optimization of pipelined processing in MPSoCs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the conference on Design, automation and test in Europe
Energy-aware scheduling for real-time multiprocessor systems with uncertain task execution time
Proceedings of the 44th annual Design Automation Conference
Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling
PATMOS '07 Proceedings of the 17th international workshop on Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Temperature-Aware Distributed Run-Time Optimization on MP-SoC Using Game Theory
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
Power Modeling in SystemC at Transaction Level, Application to a DVFS Architecture
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
Methods for power optimization in SOC-based data flow systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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With growing integration, power consumption is becoming a major issue for multi-core chips. At system level, per-core DVFS is expected to save substantial energy provided an adapted control. In this paper we propose a local on-line optimization technique to reduce energy in data-flow architecture, thanks to a Local Power Manager (LPM) using Vdd-Hopping for efficient local DVFS. The proposed control is a hybrid global and local scheme which respects throughput and latency constraints. The approach has been fully validated on a real MIMO Telecom application using a SystemC platform instrumented with power estimates. Local DVFS brings 45% power reduction compared to idle mode. When local on-line optimization benefit from computation time variations, 30% extra energy savings can be achieved.