Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC

Authors:
Ryo Watanabe;Masaaki Kondo;Masashi Imai;Hiroshi Nakamura;Takashi Nanya
Affiliations:
The University of Tokyo;The University of Tokyo;The University of Tokyo, Komaba, Meguro-City, Tokyo, Japan;The University of Tokyo;The University of Tokyo
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
2007

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Abstract

The present paper focuses on applications that are periodic and have both latency and throughput constraints. For these applications, pipeline scheduling is effective for reducing energy consumption. Thus, the present paper proposes a pipelined task scheduling method for minimizing the energy consumption of GALS MP-SoC under latency and throughput constraints. First, we model target GALS MP-SoC architecture and application tasks. We then show that the energy optimization problem under this model belongs to the class of Mixed-Integer Linear Programming. Next, we propose a new scheduling method based on simulated annealing for the purpose of solving this problem quickly. Finally, experimental results demonstrate that the proposed method achieves a significant energy reduction on a real application under a practical architecture.