Run-time voltage hopping for low-power real-time systems
Proceedings of the 37th Annual Design Automation Conference
Design and reliability challenges in nanometer technologies
Proceedings of the 41st annual Design Automation Conference
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Process and environmental variation impacts on ASIC timing
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Workload prediction and dynamic voltage scaling for MPEG decoding
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Combining system scenarios and configurable memories to tolerate unpredictability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling
PATMOS '07 Proceedings of the 17th international workshop on Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Systematic preprocessing of data dependent constructs for embedded systems
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Statistical approach in a system level methodology to deal with process variation
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on ESTIMedia'10
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Process variation and the dynamism of modern applications can degrade the expected performance of a system. Execution time can be severely affected by both factors, resulting in deadline violations and energy consumption overheads. Memory organizations, which account for a large part of the system energy and the time budgets, are especially vulnerable to process variation. Configurable - multimode - memories are a promising technology to deal with these problems, but they also introduce new issues that need to be solved. Essentially, adding configuration capabilities to the memories comes with a cost, both in memory area and control complexity; hence, we need to evaluate what is the minimum amount of re-configurability to satisfy system's constraints. In this paper, we analyze the scalability of configurable memories and highlight the relationship among mode allocation, memory mapping and data allocation.