Storage Management Programmable Process
Storage Management Programmable Process
Design and reliability challenges in nanometer technologies
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Design Style Case Study for Embedded Multi Media Compute Nodes
RTSS '04 Proceedings of the 25th IEEE International Real-Time Systems Symposium
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Combining system scenarios and configurable memories to tolerate unpredictability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Statistical static timing analysis: A survey
Integration, the VLSI Journal
Characterizing and mitigating the impact of process variations on phase change based memory systems
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
A Standardized Knobs and Monitors RTL2RTL Insertion Methodology for Fine Grain SoC Tuning
DSD '09 Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
System-level hardware-based protection of memories against soft-errors
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The impact of process variation in state of the art technology makes traditional(worst case) designs unnecessarily pessimistic, which translates to a suboptimal designs in terms of both energy consumption and performance. In this context, developing variation aware design methodologies becomes a must. These techniques should provide better performance-energy balances while the percentage of faulty products keeps controlled. Furthermore, it would be advisable to consider adaptations of the system during lifetime, in order to provide robustness against ageing. In this paper we propose a design approach which tackles process variation on the memory system by using multimode memories. At design time we perform a heuristic exploration using probabilistic models of these memories, which generates a set of system configurations that minimize energy consumption for a given set of timing constraints. The percentage of systems that will satisfy these deadlines, even under process variation, is taken as a design parameter. Additionally, if system monitors are available, a setup stage optimizes the initial set of configurations for the actual memory parameters. Our simulations show that this methodology provides significant energy savings while still meeting timing constraints