Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Mismatch Characterization of Submicron MOS Transistors
Analog Integrated Circuits and Signal Processing
Proceedings of the conference on Design, automation and test in Europe - Volume 1
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Statistically Aware SRAM Memory Array Design
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Impact of process variations on multicore performance symmetry
Proceedings of the conference on Design, automation and test in Europe
Combining system scenarios and configurable memories to tolerate unpredictability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Statistical approach in a system level methodology to deal with process variation
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on ESTIMedia'10
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Variability is becoming a serious problem in process technology for nanometer technology nodes. The increasing difficulty in controlling the uniformity of critical process parameters (e.g. doping levels) in the smaller devices, makes the electrical properties of such scaled devices much less predictable than in the past. In this paper, we study how these technology effects influence the energy and delay of a SRAM module. Despite the implications in the correct operation of the module, in practically all cases the affected memory implementations become also slower while consuming on average more energy than nominally. This is partly counter-intuitive and no existing literature desribes this in a systematic generic way for SRAMs. In this paper, we identify and illustrate the different mechanisms behind this unexpected behavior and quantify the impact of these effects for on-chip SRAMs at the 65nm technology node.