Mathematical Statistics with Mathematica with CD-ROM
Mathematical Statistics with Mathematica with CD-ROM
Statistical estimation of leakage current considering inter- and intra-die process variation
Proceedings of the 2003 international symposium on Low power electronics and design
Proceedings of the 2004 international symposium on Low power electronics and design
Ultralow-power SRAM technology
IBM Journal of Research and Development
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Statistical design and optimization of SRAM cell for yield enhancement
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Variability in sub-100nm SRAM designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Strategies for improving the parametric yield and profits of 3D ICs
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Parametric yield management for 3D ICs: Models and strategies for improvement
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Proceedings of the 7th ACM international conference on Computing frontiers
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Increasing process-parameter variations due to technology scaling to nanometer nodes have a significant impact on the circuit design flow. As shown repeatedly in previous work, a worst-case design approach is no longer feasible to guarantee a yielding design. Furthermore, the study of these process-parameter variations on the distributions of performance parameters has been done extensively in the past. However, this will not improve the circuit design unless the statistical information is considered during the optimization of the design. In this paper, we propose a method to minimize the leakage power of a SRAM cell while satisfying conflicting functionality and delay constraints, under these technology variations. Additionally, this method generates power-stability tradeoffs to optimize the circuit for a given yield at design time. Even at cell level, statistically aware design allows both minimal standby leakage power and minimal area.