Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization

Authors:
Rahul Rao;Kanak Agarwal;Anirudh Devgan;Kevin Nowka;Dennis Sylvester;Richard Brown
Affiliations:
University of Michigan, Ann Arbor, MI;University of Michigan, Ann Arbor, MI;Austin Research Laboratories, IBM, Austin, TX;Austin Research Laboratories, IBM, Austin, TX;University of Michigan, Ann Arbor, MI;University of Utah, Salt Lake City, UT
Venue:
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Year:
2005

Citing 5
Cited 6

Design of High-Performance Microprocessor Circuits

Design of High-Performance Microprocessor Circuits
Modeling and analysis of leakage power considering within-die process variations

Proceedings of the 2002 international symposium on Low power electronics and design
Parameter variations and impact on circuits and microarchitecture

Proceedings of the 40th annual Design Automation Conference
Speed Binning with Path Delay Test in 150-nm Technology

IEEE Design & Test
Delay Defect Characteristics and Testing Strategies

IEEE Design & Test

Statistically Aware SRAM Memory Array Design

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Invited paper: Variability in nanometer CMOS: Impact, analysis, and minimization

Integration, the VLSI Journal
Statistical Modeling and Analysis of Static Leakage and Dynamic Switching Power

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Analytical model-based technique for efficient evaluation of noise robustness considering parameter variations

Analog Integrated Circuits and Signal Processing
A centralized supply voltage and local body bias-based compensation approach to mitigate within-die process variation

Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design

Quantified Score

Hi-index	0.00

Visualization

Abstract

Parametric yield loss has become a serious concern in leakage dominated technologies. In this paper, we discuss the impact of leakage on parametric yield and show that leakage can cause yield window to shrink by imposing a two-sided constraint on the window. We present a mathematical framework for yield estimation under device process variation for a given power and frequency constraints. The model is validated against Monte Carlo simulations for an industry process and is shown to have typical error of less than 5%. We then demonstrate the importance of optimal supply voltage selection for yield maximization. We also investigate the sensitivity of parametric yield to applied frequency and power constraints. Finally, we apply the proposed framework to the problem of maximizing the shipping frequency in the presence of given yield and power constraints.