Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
New approach in gate-level glitch modelling
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Death, taxes and failing chips
Proceedings of the 40th annual Design Automation Conference
Selective gate-length biasing for cost-effective runtime leakage control
Proceedings of the 41st annual Design Automation Conference
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
New Generation of Predictive Technology Model for Sub-45nm Design Exploration
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Impact of Gate-Length Biasing on Threshold-Voltage Selection
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Statistical analysis of SRAM cell stability
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Parameter-Variation-Aware Analysis for Noise Robustness
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Harmony: static noise analysis of deep submicron digital integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we present an accurate method for analytical derivation of noise rejection curves (NRCs) and the associated noise susceptibility metric in the presence of variations in process and environmental parameters. The method involves modeling of the pull-up and pull-down resistances of combinational gates using approximated BSIM4 model-based device equations. Comparisons of the analytical model with circuit simulations show that the impact of parameter variations on the noise susceptibility is accurately captured by our model. The average (maximum) error associated with the noise susceptibility is found to be as low as 2.6% (6.7%). Our model can predict the noise susceptibility under parameter variations more than five orders of magnitude faster than circuit simulations, which makes it suitable for design optimization for noise robustness.