Aggressor alignment for worst-case coupling noise
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Multi-center congestion estimation and minimization during placement
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Proceedings of the 37th Annual Design Automation Conference
Interconnect parasitic extraction in the digital IC design methodology
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Body-voltage estimation in digital PD-SOI circuits and its application to static timing analysis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Incremental delay change due to crosstalk noise
Proceedings of the 2002 international symposium on Physical design
Timed pattern generation for noise-on-delay calculation
Proceedings of the 39th annual Design Automation Conference
Practical considerations in RLCK crosstalk analysis for digital integrated circuits
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Crosstalk Measurement Technique for CMOS ICs
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Efficient crosstalk noise modeling using aggressor and tree reductions
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Physical synthesis methodology for high performance microprocessors
Proceedings of the 40th annual Design Automation Conference
Interconnect and noise immunity design for the Pentium 4 processor
Proceedings of the 40th annual Design Automation Conference
Identification of Crosstalk Switch Failures in Domino CMOS Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
CAD Issues for CMOS VLSI Design in SOI
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
A High-Speed Transceiver Architecture Implementable as Synthesizable IP Core
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Noise characterization of static CMOS gates
Proceedings of the 41st annual Design Automation Conference
EM Wave Coupling Noise Modeling Based on Chebyshev Approximation and Exact Moment Formulation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Modeling the Non-Linear Behavior of Library Cells for an Accurate Static Noise Analysis
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Noise Library Characterization for Large Capacity Static Noise Analysis Tools
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A Comprehensive Methodology for Noise Characterization of ASIC Cell Libraries
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A complete methodology for an accurate static noise analysis
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Fast Sequential Cell Noise Immunity Characterization Using Meta-stable Point of Feedback Loop
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Monotonic static CMOS tradeoffs in sub-100nm technologies
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Cell broadband engine processor: design and implementation
IBM Journal of Research and Development
Noise separation in analog integrated circuits using independent component analysis technique
Integrated Computer-Aided Engineering
Analog Integrated Circuits and Signal Processing
The circuit and physical design of the POWER4 microprocessor
IBM Journal of Research and Development
IBM eServer z900 high-frequency microprocessor technology, circuits, and design methodology
IBM Journal of Research and Development
Cache vulnerability equations for protecting data in embedded processor caches from soft errors
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
Performability/energy tradeoff in error-control schemes for on-chip networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Receiver modeling for static functional crosstalk analysis
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Crosstalk waveform modeling using wave fitting
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
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As technology scales into the deep submicron regime, noise immunity is becoming a metric of comparable importance to area, timing, and power for the analysis and design of very large scale integrated (VLSI) systems. A metric for noise immunity is defined, and a static noise analysis methodology based on this noise-stability metric is introduced to demonstrate how noise can be analyzed systematically on a full-chip basis using simulation-based transistor-level analysis. We then describe Harmony, a two-level (macro and global) hierarchical implementation of static noise analysis. At the macro level, simplified interconnect models and timing assumptions guide efficient analysis. The global level involves a careful combination of static noise analysis, static timing analysis, and detailed interconnect macromodels based on reduced-order modeling techniques. We describe how the interconnect macromodels are practically employed to perform coupling analysis and how timing constraints can be used to limit pessimism in the analysis