Harmony: static noise analysis of deep submicron digital integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DVS for On-Chip Bus Designs Based on Timing Error Correction
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
EM Wave Coupling Noise Modeling Based on Chebyshev Approximation and Exact Moment Formulation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
NostraXtalk: a predictive framework for accurate static timing analysis in udsm vlsi circuits
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Noise separation in analog integrated circuits using independent component analysis technique
Integrated Computer-Aided Engineering
Compound noise separation in digital circuits using blind source separation
Microelectronics Journal
Reducing interconnect delay uncertainty via hybrid polarity repeater insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FA-STAC: An algorithmic framework for fast and accurate coupling aware static timing analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper describes the key challenges, design methods, CAD and learnings in the area of interconnect and noise immunity design for the Intel Pentium 4 processor.This high frequency (currently at 3 Ghz with 6 Ghz execution core) design required aggressive domino, pulsed and other novel high speed circuit families that are very noise sensitive. Controlling interconnect delay, capacitive and inductive coupling is of paramount importance at such high frequencies and edge rates, made more difficult by die cost pressures of a high volume chip.We first describe our wire/ repeater design methods and silicon results. We then describe a proprietary noise simulator (NoisePad) and our noise robust cell library, both of which were critical to noise robustness. Finally,our test chip results and use of a distributed power grid to manage inductance is described.