Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Partial bus-invert coding for power optimization of system level bus
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Working-zone encoding for reducing the energy in microprocessor address buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ISPD '00 Proceedings of the 2000 international symposium on Physical design
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ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
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ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
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ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Odd/even bus invert with two-phase transfer for buses with coupling
Proceedings of the 2002 international symposium on Low power electronics and design
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Proceedings of the 2002 international symposium on Low power electronics and design
Coupling-driven signal encoding scheme for low-power interface design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
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Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
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Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
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COMPCON '97 Proceedings of the 42nd IEEE International Computer Conference
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
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ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
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Proceedings of the 30th annual international symposium on Computer architecture
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HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
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Proceedings of the conference on Design, automation and test in Europe - Volume 1
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Proceedings of the 2004 international symposium on Low power electronics and design
A robust edge encoding technique for energy-efficient multi-cycle interconnect
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Reducing interconnect delay uncertainty via hybrid polarity repeater insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A robust edge encoding technique for energy-efficient multi-cycle interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We propose various low-latency spatial encoder circuits based on bus-invert coding for reducing peak energy and current in on-chip buses with minimum penalty on total latency. The encoders are implemented in dual-rail domino logic with interfaces for static inputs and static buses. A spatial and temporally encoded dynamic bus technique is also proposed for higher performance targets. Comparisons to standard on-chip buses of various lengths with optimal repeater configurations at the 130-nm node show the energy-delay and peak current-delay design space in which the different encoder circuits are beneficial. A 9-mm spatially encoded static bus exhibits peak energy gains beyond that achievable through repeater optimization for a single-cycle operation at 1 GHz, with delay and energy overhead of the encoding included. For throughput-constrained buses, the spatially encoded static bus can provide up to 31% reduction in peak energy, while the spatially and temporally encoded dynamic bus yields peak current reductions of more than 50% for all bus lengths. The encoder circuits show good scaling properties since the performance penalty from encoding decreases with scaled interconnects.