Power estimation for architectural exploration of HW/SW communication on system-level buses
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Synthesis of low-overhead interfaces for power-efficient communication over wide buses
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Selective instruction compression for memory energy reduction in embedded systems
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
System-level power optimization: techniques and tools
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
System-level power optimization: techniques and tools
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Data and memory optimization techniques for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Energy reduction in queues and stacks by adaptive bitwidth compression
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Low-energy for deep-submicron address buses
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Reducing energy consumption of video memory by bit-width compression
Proceedings of the 2002 international symposium on Low power electronics and design
An energy-conscious algorithm for memory port allocation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Weight-Based Bus-Invert Coding for Low-Power Applications
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
A Low Power-Delay Product Page-Based Address Bus Coding Method
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
An evolutionary approach for reducing the energy in address buses
ISICT '03 Proceedings of the 1st international symposium on Information and communication technologies
Power Aware Interface Synthesis for Bus-Based SoC Designs
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Power-Performance System-Level Exploration of a MicroSPARC2-Based Embedded Architecture
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Abridged addressing: a low power memory addressing strategy
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Power optimal MTCMOS repeater insertion for global buses
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Timing-driven row-based power gating
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Component deployment optimisation with bayesian learning
Proceedings of the 14th international ACM Sigsoft symposium on Component based software engineering
Architecture-driven reliability optimization with uncertain model parameters
Journal of Systems and Software
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This paper presents a solution to the problem of reducing the power dissipated by a digital system containing an intellectual proprietary core processor which repeatedly executes a special-purpose program. The proposed method relies on a novel, application-dependent low-power address bus encoding scheme. The analysis of the execution traces of a given program allows an accurate computation of the correlations that may exist between blocks of bits in consecutive patterns; this information can be successfully exploited to determine an encoding which sensibly reduces the bus transition activity. Experimental results, obtained on a set of special-purpose applications, are very satisfactory; reductions of the bus activity up to 64.8% (41.8% on average) have been achieved over the original address streams. In addition, data concerning the quality and the performance of the automatically synthesized encoding/decoding circuits, as well as the results obtained for a realistic core-based design, indicate the practical usefulness of the proposed power optimization strategy.