Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of a low power video decompression chip set for portable applications
Journal of VLSI Signal Processing Systems - Special issue on technologies for wireless computing
Low power motion estimation design using adaptive pixel truncation
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
The energy efficiency of IRAM architectures
Proceedings of the 24th annual international symposium on Computer architecture
Power optimization of core-based systems by address bus encoding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Working-zone encoding for reducing the energy in microprocessor address buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Conforming inverted data store for low power memory
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Dynamic zero compression for cache energy reduction
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
A low energy cache design for multimedia applications exploiting set access locality
Journal of Systems Architecture: the EUROMICRO Journal
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A new architectural technique to reduce energy dissipation of video memory is proposed. Unlike existing approaches, the technique exploits the pixel correlation in video sequences, dynamically adjusting the memory bit-width to the number of bits changed per pixel. Instead of treating the data bits independently, we group the most significant bits together, activating the corresponding group of bit-lines adaptively to data variation. The method is not restricted to the specific bit-patterns nor depends on the storage phase. It works equally well on read and write accesses, as well as during precharging. Simulation results show that using this method we can reduce the total energy consumption of video memory by 20% without affecting the picture quality.