Hitting the memory wall: implications of the obvious
ACM SIGARCH Computer Architecture News
Missing the memory wall: the case for processor/memory integration
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
The design of a high performance low power microprocessor
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
New DRAM Technologies: A Comprehensive Analysis of the New Architecture
New DRAM Technologies: A Comprehensive Analysis of the New Architecture
IEEE Micro
Energy efficient CMOS microprocessor design
HICSS '95 Proceedings of the 28th Hawaii International Conference on System Sciences
Performance Characterization of the Alpha 21164 Microprocessor Using TP and SPEC Workloads
HPCA '96 Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture
Microservers: a new memory semantics for massively parallel computing
ICS '99 Proceedings of the 13th international conference on Supercomputing
Efficient management of memory hierarchies in embedded DRAM systems
ICS '99 Proceedings of the 13th international conference on Supercomputing
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Exploiting ILP in page-based intelligent memory
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Quantifying the energy consumption of a pocket computer and a Java virtual machine
Proceedings of the 2000 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
The performance and energy consumption of three embedded real-time operating systems
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Reducing energy consumption of video memory by bit-width compression
Proceedings of the 2002 international symposium on Low power electronics and design
An adaptive chip-multiprocessor architecture for future mobile terminals
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
IEEE Micro
Architectural Support for Data-intensive Applications
IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium
Reordering Memory Bus Transactions for Reduced Power Consumption
LCTES '00 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
Exploiting On-Chip Memory Bandwidth in the VIRAM Compiler
IMS '00 Revised Papers from the Second International Workshop on Intelligent Memory Systems
Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems
IMS '00 Revised Papers from the Second International Workshop on Intelligent Memory Systems
Micro-architecture design and control speculation for energy reduction
Power aware computing
Reducing Cost and Tolerating Defects in Page-based Intelligent Memory
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Graphics for the masses: a hardware rasterization architecture for mobile phones
ACM SIGGRAPH 2003 Papers
The Performance and Energy Consumption of Embedded Real-Time Operating Systems
IEEE Transactions on Computers
A Low Power Strategy for Future Mobile Terminals
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Analysis and Modeling of Advanced PIM Architecture Design Tradeoffs
Proceedings of the 2004 ACM/IEEE conference on Supercomputing
An energy efficient garbage collector for java embedded devices
LCTES '05 Proceedings of the 2005 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
On designing a low-power garbage collector for java embedded devices: a case study
Proceedings of the 2005 ACM symposium on Applied computing
Adaptive and flexible dictionary code compression for embedded applications
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Proceedings of the 7th annual IEEE/ACM International Symposium on Code Generation and Optimization
Algorithms and theory of computation handbook
A service framework for energy-aware monitoring and VM management in Clouds
Future Generation Computer Systems
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Portable systems demand energy efficiency in order to maximize battery life. IRAM architectures, which combine DRAM and a processor on the same chip in a DRAM process, are more energy efficient than conventional systems. The high density of DRAM permits a much larger amount of memory on-chip than a traditional SRAM cache design in a logic process. This allows most or all IRAM memory accesses to be satisfied on-chip. Thus there is much less need to drive high-capacitance off-chip buses, which contribute significantly to the energy consumption of a system. To quantify this advantage we apply models of energy consumption in DRAM and SRAM memories to results from cache simulations of applications reflective of personal productivity tasks on low power systems. We find that IRAM memory hierarchies consume as little as 22% of the energy consumed by a conventional memory hierarchy for memory-intensive applications, while delivering comparable performance. Furthermore, the energy consumed by a system consisting of an IRAM memory hierarchy combined with an energy efficient CPU core is as little as 40% of that of the same CPU core with a traditional memory hierarchy.