Clustered voltage scaling technique for low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Energy optimization of multi-level processor cache architectures
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Cache design trade-offs for power and performance optimization: a case study
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Assigning confidence to conditional branch predictions
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
The energy efficiency of IRAM architectures
Proceedings of the 24th annual international symposium on Computer architecture
The filter cache: an energy efficient memory structure
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor
Digital Technical Journal
Confidence estimation for speculation control
Proceedings of the 25th annual international symposium on Computer architecture
Pipeline gating: speculation control for energy reduction
Proceedings of the 25th annual international symposium on Computer architecture
Selective eager execution on the PolyPath architecture
Proceedings of the 25th annual international symposium on Computer architecture
Value locality and speculative execution
Value locality and speculative execution
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Low-Power CMOS Design
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Branch Prediction Using Selective Branch Inversion
PACT '99 Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques
Slack: maximizing performance under technological constraints
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
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Conventional wisdom states that the best way to design an energy-efficient microprocessor is to design it for high performance, since a high performance processor will complete a task quicker than an energy-conscious design. However, our research group has found ways to reduce energy without impacting performance by controlling the amount of speculation used by the processor in its quest for performance.