Energy optimization of multi-level processor cache architectures

  • Authors:
  • Uming Ko;Poras T. Balsara;Ashwini K. Nanda

  • Affiliations:
  • Texas Instruments Incorporated, P. O. Box 655303, M/S 8316, Dallas, TX;Department of Electrical Engineering, University of Texas at Dallas, P. O. Box 830688, Richardson, TX;Texas Instruments Incorporated, P. O. Box 655303, M/S 8316, Dallas, TX

  • Venue:
  • ISLPED '95 Proceedings of the 1995 international symposium on Low power design
  • Year:
  • 1995

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Abstract