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Cache performance of operating system and multiprogramming workloads
ACM Transactions on Computer Systems (TOCS)
Column-associative caches: a technique for reducing the miss rate of direct-mapped caches
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Cache designs with partial address matching
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Energy optimization of multi-level processor cache architectures
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Cache design trade-offs for power and performance optimization: a case study
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The filter cache: an energy efficient memory structure
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
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Way-predicting set-associative cache for high performance and low energy consumption
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Selective cache ways: on-demand cache resource allocation
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
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ACM Transactions on Computer Systems (TOCS)
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SH3: High Code Density, Low Power
IEEE Micro
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Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques
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GLS '98 Proceedings of the Great Lakes Symposium on VLSI '98
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HPCA '96 Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture
Just Say No: Benefits of Early Cache Miss Determination
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
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ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
A highly configurable cache architecture for embedded systems
Proceedings of the 30th annual international symposium on Computer architecture
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Transactions on High-Performance Embedded Architectures and Compilers II
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Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
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HiPEAC'07 Proceedings of the 2nd international conference on High performance embedded architectures and compilers
Location cache design and performance analysis for chip multiprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low power design of precomputation-based content-addressable memory
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An energy-efficient L2 cache architecture using way tag information under write-through policy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Journal of Parallel and Distributed Computing
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While set-associative caches incur fewer misses than direct-mapped caches, they typically have slower hit times and higher power consumption, when multiple tag and data banks are probed in parallel. This paper presents the location cache structure which significantly reduces the power consumption for large set-associative caches. We propose to use a small cache, called location cache to store the location of future cache references. If there is a hit in the location cache, the supported cache is accessed as a direct-mapped cache. Otherwise, the supported cache is referenced as a conventional set-associative cache.The worst case access latency of the location cache system is the same as that of a conventional cache. The location cache is virtually indexed so that operations on it can be performed in parallel with the TLB address translation. These advantages make it ideal for L2 cache systems where traditional way-predication strategies perform poorly.We used the CACTI cache model to evaluate the power con-sumption and access latency of proposed cache architecture. Simplescalar CPU simulator was used to produce final results. It is shown that the proposed location cache architecture is power-efficient. In the simulated cache configurations, up-to 47% of cache accessing energy and 25% of average cache access latency can be reduced.