Cache design trade-offs for power and performance optimization: a case study
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Way-predicting set-associative cache for high performance and low energy consumption
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
A low power unified cache architecture providing power and performance flexibility (poster session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
SH3: High Code Density, Low Power
IEEE Micro
A highly configurable cache architecture for embedded systems
Proceedings of the 30th annual international symposium on Computer architecture
Location cache: a low-power L2 cache system
Proceedings of the 2004 international symposium on Low power electronics and design
Soft error and energy consumption interactions: a data cache perspective
Proceedings of the 2004 international symposium on Low power electronics and design
Computer Architecture, Fourth Edition: A Quantitative Approach
Computer Architecture, Fourth Edition: A Quantitative Approach
Soft Error Rates in 65nm SRAMs--Analysis of new Phenomena
IOLTS '07 Proceedings of the 13th IEEE International On-Line Testing Symposium
Balancing Performance and Reliability in the Memory Hierarchy
ISPASS '05 Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2005
An energy-efficient L2 cache architecture using way tag information under write-through policy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
Write-through policy employed in many high-performance microprocessors provides good tolerance to soft errors in cache systems. However, it also incurs large energy overhead due to the increased accesses to caches at the lower level (e.g., the L2 cache) during write operations. In this paper, we propose a new cache architecture referred to as way-tagged cache to improve the energy efficiency of write-through cache systems. By maintaining the way tags of the L2 cache in the L1 cache during read operations, the proposed technique enables the L2 cache to work in an equivalent direct-mapping manner during write hits, which account for the majority of L2 cache accesses. This leads to significant energy reduction. Simulation results on the SPEC CPU2000 benchmarks demonstrate that the proposed technique achieves 65.4% energy savings on average with about 0.02% area overhead and no performance degradation.